Makefile Syntax

A makefile can contain rules, macro definitions (see Macros ), and comments. There are two kinds of rules: inference rules and target rules. The make utility contains a set of built-in inference rules. If the -r option is present, the built-in rules are not used and the suffix list is cleared. Additional rules of both types can be specified in a makefile. If a rule or macro is defined more than once, the value of the rule or macro will be that of the last one specified. Comments start with a number sign (#) and continue until an unescaped newline character is reached.

By default, the following files are tried in sequence: ./makefile, ./Makefile, ./s.makefile, SCCS/s.makefile, ./s.Makefile, and SCCS/s.Makefile.

The -f option directs make to ignore any of these default files and use the specified argument as a makefile instead. If the "-" argument is specified, standard input will be used.

The term makefile is used to refer to any rules provided by the user, whether in ./makefile or its variants, or specified by the -f option.

The rules in makefiles consist of the following types of lines: target rules, including special targets (see Target Rules); inference rules (see Inference Rules); macro definitions (see Macros); empty lines; and comments. Comments start with a number sign (#) and continue until an unescaped newline character is reached.

When an escaped newline character (one preceded by a backslash) is found anywhere in the makefile, it is replaced, along with any leading white space on the following line, with a single space character.

Makefile Execution

Command lines are processed one at a time by writing the command line to the standard output (unless one of the conditions listed below under "@" suppresses the writing) and executing the commands in the line. A tab character may precede the command to standard output. Commands will be executed by passing the command line to the command interpreter in the same manner as if the string were the argument to the XSH specification system(3) function.

The environment for the command being executed will contain all of the variables in the environment of make. The macros from the command line to make will be added to make 's environment. Other implementation-dependent variables may also be added to make 's environment. If any command-line macro has been defined elsewhere, the command-line value will overwrite the existing value. If the MAKEFLAGS variable is not set in the environment in which make was invoked, in the makefile or on the command line, it will be created by make, and will contain all options specified on the command line except for the -f and -p options. It may also contain implementation-dependent options.

By default, when make receives a non-zero status from the execution of a command, it terminates with an error message to standard error.

Command lines can have one or more of the following prefixes: a hyphen (-), an at sign (@), or a plus sign (+). These modify the way in which make processes the command. When a command is written to standard output, the prefix is not included in the output.

-

If the command prefix contains a hyphen, or the -i option is present, or the special target .IGNORE has either the current target as a prerequisite or has no prerequisites, any error found while executing the command will be ignored.

@

If the command prefix contains an at sign and the command-line -n option is not specified, or the -s option is present, or the special target .SILENT has either the current target as a prerequisite or has no prerequisites, the command will not be written to standard output before it is executed.

+

If the command prefix contains a plus sign, this indicates a command line that will be executed even if -n , -q or -t is specified.

Target Rules

Target rules are formatted as follows:

target [target...]: [prerequisite...][;command]
[<tab>command]
<tab>command
...]

line that does not begin with <tab>

Target entries are specified by a blank-character-separated, non-null list of targets, then a colon, then a blank-character-separated, possibly empty list of prerequisites. Text following a semicolon, if any, and all following lines that begin with a tab character, are command lines to be executed to update the target. The first non-empty line that does not begin with a tab character or "#" begins a new entry. An empty or blank line, or a line beginning with "#", may begin a new entry.

Applications must select target names from the set of characters consisting solely of periods, underscores, digits and alphabetics from the portable character set (see the XBD specification, charset(7) ). Implementations may allow other characters in target names as extensions. The interpretation of targets containing the characters "%" and """ is implementation-dependent.

A target that has prerequisites, but does not have any commands, can be used to add to the prerequisite list for that target. Only one target rule for any given target can contain commands.

Lines that begin with one of the following are called special targets and control the operation of make:

.DEFAULT

If the makefile uses this special target, it must be specified with commands, but without prerequisites. The commands will be used by make if there are no other rules available to build a target.

.IGNORE

Prerequisites of this special target are targets themselves; this will cause errors from commands associated with them to be ignored in the same manner as specified by the -i option. Subsequent occurrences of .IGNORE add to the list of targets ignoring command errors. If no prerequisites are specified, make will behave as if the -i option had been specified and errors from all commands associated with all targets will be ignored.

.POSIX

This special target must be specified without prerequisites or commands. If it appears before the first non-comment line in the makefile, make will process the makefile as specified by this section; otherwise, the behaviour of make is unspecified.

.PRECIOUS

Prerequisites of this special target will not be removed if make receives one of the asynchronous events explicitly described in the ASYNCHRONOUS EVENTS section. Subsequent occurrences of .PRECIOUS add to the list of precious files. If no prerequisites are specified, all targets in the makefile will be treated as if specified with .PRECIOUS .

.SCCS_GET

This special target must be specified without prerequisites. If this special target is included in a makefile, the commands specified with this target replace the default commands associated with this special target. (See Default Rules .) The commands specified with this target are used to get all SCCS files that are not found in the current directory. When source files are named in a dependency list, make treats them just like any other target. Because the source file is presumed to be present in the directory, there is no need to add an entry for it to the makefile. When a target has no dependencies, but is present in the directory, make assumes that that file is up-to-date. If, however, an SCCS file named SCCS/s. source_file is found for a target source_file , make does some additional checking to assure that the target is up-to-date. If the target is missing, or if the SCCS file is newer, make automatically issues the commands specified for the .SCCS_GET special target to retrieve the most recent version. However, if the target is writable by anyone, make does not retrieve a new version.

.SILENT

Prerequisites of this special target are targets themselves; this causes commands associated with them to not be written to the standard output before they are executed. Subsequent occurrences of .SILENT add to the list of targets with silent commands. If no prerequisites are specified, make will behave as if the -s option had been specified and no commands or touch messages associated with any target will be written to standard output.

.SUFFIXES

Prerequisites of .SUFFIXES are appended to the list of known suffixes and are used in conjunction with the inference rules (see Inference Rules ). If .SUFFIXES does not have any prerequisites, the list of known suffixes will be cleared. Makefiles must not associate commands with .SUFFIXES .

Targets with names consisting of a leading period followed by the upper-case letters POSIX and then any other characters are reserved for future standardisation. Targets with names consisting of a leading period followed by one or more upper-case letters are reserved for implementation extensions.

Macros

Macro definitions are in the form:

string1 "=" [ string2 ]

The macro named string1 is defined as having the value of string2, where string2 is defined as all characters, if any, after the equal sign, up to a comment character (#) or an unescaped newline character. Any blank characters immediately before or after the equal sign will be ignored.

Subsequent appearances of $( string1 ) or ${ string1 } are replaced by string2. The parentheses or braces are optional if string1 is a single character. The macro $$ is replaced by the single character "$".

Applications must select macro names from the set of characters consisting solely of periods, underscores, digits and alphabetics from the portable character set (see the XBD specification, charset(7) ). A macro name cannot contain an equal sign. Implementations may allow other characters in macro names as extensions.

Macros can appear anywhere in the makefile. Macros in target lines will be evaluated when the target line is read. Macros in command lines will be evaluated when the command is executed. Macros in macro definition lines will not be evaluated until the new macro being defined is used in a rule or command. A macro that has not been defined will evaluate to a null string without causing any error condition.

The forms $( string1 [: subst1 =[ subst2 ]]) or ${ string1 [: subst1 =[ subst2 ]]} can be used to replace all occurrences of subst1 with subst2 when the macro substitution is performed. The subst1 to be replaced is recognised when it is a suffix at the end of a word in string1 (where a word, in this context, is defined to be a string delimited by the beginning of the line, a blank or newline character).

Macro assignments will be accepted from the sources listed below, in the order shown. If a macro name already exists at the time it is being processed, the newer definition will replace the existing definition.

1. Macros defined in make 's built-in inference rules.
2. The contents of the environment, including the variables with null values, in the order defined in the environment.
3. Macros defined in the makefiles, processed in the order specified.
4. Macros specified on the command line. It is unspecified whether the internal macros defined in Internal Macros are accepted from the command line.

If the -e option is specified, the order of processing sources items 2 and 3 will be reversed.

The SHELL macro is treated specially. It is provided by make and set to the pathname of the shell command language interpreter (see sh). The SHELL environment variable will not affect the value of the SHELL macro. If SHELL is defined in the makefile or is specified on the command line, it will replace the original value of the SHELL macro, but will not affect the SHELL environment variable. Other effects of defining SHELL in the makefile or on the command line are implementation-dependent.

Inference Rules

Inference rules are formatted as follows:

target:
<tab>command
[<tab>command]
...

line that does not begin with <tab> or #

The target portion must be a valid target name (see Target Rules) of the form .s2 or .s1.s2 (where .s1 and .s2 are suffixes that have been given as prerequisites of the .SUFFIXES special target and s1 and s2 do not contain any slashes or periods.) If there is only one period in the target, it is a single-suffix inference rule. Targets with two periods are double-suffix inference rules. Inference rules can have only one target before the colon.

The makefile must not specify prerequisites for inference rules; no characters other than white space can follow the colon in the first line, except when creating the empty rule, described below. Prerequisites are inferred, as described below.

Inference rules can be redefined. A target that matches an existing inference rule will overwrite the old inference rule. An empty rule can be created with a command consisting of simply a semicolon (that is, the rule still exists and is found during inference rule search, but since it is empty, execution has no effect). The empty rule also can be formatted as follows: rule: ; where zero or more blank characters separate the colon and semicolon.

The make utility uses the suffixes of targets and their prerequisites to infer how a target can be made up-to-date. A list of inference rules defines the commands to be executed. By default, make contains a built-in set of inference rules. Additional rules can be specified in the makefile.

The special target .SUFFIXES contains as its prerequisites a list of suffixes that are to be used by the inference rules. The order in which the suffixes are specified defines the order in which the inference rules for the suffixes are used. New suffixes will be appended to the current list by specifying a .SUFFIXES special target in the makefile. A .SUFFIXES target with no prerequisites will clear the list of suffixes. An empty .SUFFIXES target followed by a new .SUFFIXES list is required to change the order of the suffixes.

Normally, the user would provide an inference rule for each suffix. The inference rule to update a target with a suffix .s1 from a prerequisite with a suffix .s2 is specified as a target .s2.s1. The internal macros provide the means to specify general inference rules. (See Internal Macros.)

When no target rule is found to update a target, the inference rules are checked. The suffix of the target ( .s1) to be built is compared to the list of suffixes specified by the .SUFFIXES special targets. If the .s1 suffix is found in .SUFFIXES, the inference rules are searched in the order defined for the first .s2.s1 rule whose prerequisite file ( $* .s2) exists. If the target is out-of-date with respect to this prerequisite, the commands for that inference rule are executed.

If the target to be built does not contain a suffix and there is no rule for the target, the single suffix inference rules will be checked. The single-suffix inference rules define how to build a target if a file is found with a name that matches the target name with one of the single suffixes appended. A rule with one suffix .s2 is the definition of how to build target from target.s2. The other suffix ( .s1) is treated as null.

A tilde (~) in the above rules refers to an SCCS file in the current directory. Thus, the rule .c~.o would transform an SCCS C-language source file into an object file ( .o). Because the s. of the SCCS files is a prefix, it is incompatible with make 's suffix point of view. Hence, the ~ is a way of changing any file reference into an SCCS file reference.

Libraries

If a target or prerequisite contains parentheses, it will be treated as a member of an archive library. For the lib ( member .o) expression lib refers to the name of the archive library and member .o to the member name. The member must be an object file with the .o suffix. The modification time of the expression is the modification time for the member as kept in the archive library. See ar(1) . The .a suffix refers to an archive library. The .s2 .a rule is used to update a member in the library from a file with a suffix .s2 .

Internal Macros

The make utility maintains five internal macros that can be used in target and inference rules. In order to clearly define the meaning of these macros, some clarification of the terms target rule , inference rule , target and prerequisite is necessary.

Target rules are specified by the user in a makefile for a particular target. Inference rules are user- or make -specified rules for a particular class of target names. Explicit prerequisites are those prerequisites specified in a makefile on target lines. Implicit prerequisites are those prerequisites that are generated when inference rules are used. Inference rules are applied to implicit prerequisites or to explicit prerequisites that do not have target rules defined for them in the makefile. Target rules are applied to targets specified in the makefile.

Before any target in the makefile is updated, each of its prerequisites (both explicit and implicit) will be updated. This is accomplished by recursively processing each prerequisite. Upon recursion, each prerequisite becomes a target itself. Its prerequisites in turn are processed recursively until a target is found that has no prerequisites, at which point the recursion stops. The recursion then backs up, updating each target as it goes.

In the definitions that follow, the word target refers to one of:

• a target specified in the makefile
• an explicit prerequisite specified in the makefile that becomes the target when make processes it during recursion
• an implicit prerequisite that becomes a target when make processes it during recursion.

In the definitions that follow, the word prerequisite refers to one o the following:

• an explicit prerequisite specified in the makefile for a particular target
• an implicit prerequisite generated as a result of locating an appropriate inference rule and corresponding file that matches the suffix of the target.

The five internal macros are:

$@

The $@ evaluates to the full target name of the current target, or the archive filename part of a library archive target. It is evaluated for both target and inference rules. For example, in the .c.a inference rule, $@ represents the out-of-date .a file to be built. Similarly, in a makefile target rule to build lib.a from file.c , $@ represents the out-of-date lib.a .

$%

The $% macro is evaluated only when the current target is an archive library member of the form libname ( member .o ). In these cases, $@ evaluates to libname and $% evaluates to member .o . The $% macro is evaluated for both target and inference rules. For example, in a makefile target rule to build lib.a(file.o) , $% represents file.o as opposed to $@, which represents lib.a .

$?

The $? macro evaluates to the list of prerequisites that are newer than the current target. It is evaluated for both target and inference rules. For example, in a makefile target rule to build prog from file1.o , file2.o and file3.o , and where prog is not out of date with respect to file1.o , but is out of date with respect to file2.o and file3.o , $? represents file2.o and file3.o .

$<

In an inference rule, $< evaluates to the filename whose existence allowed the inference rule to be chosen for the target. In the .DEFAULT rule, the $< macro evaluates to the current target name. The $< macro is evaluated only for inference rules. For example, in the .c.a inference rule, $< represents the prerequisite .c file.

$*

The $* macro evaluates to the current target name with its suffix deleted. It is evaluated at least for inference rules. For example, in the .c.a inference rule, $*.o represents the out-of-date .o file that corresponds to the prerequisite .c file.

Each of the internal macros has an alternative form. When an upper-case D or F is appended to any of the macros, the meaning is changed to the directory part for D and filename part for F. The directory part is the path prefix of the file without a trailing slash; for the current directory, the directory part is ".". When the $? macro contains more than one prerequisite filename, the $(?D) and $(?F) (or ${?D} and ${?F}) macros expand to a list of directory name parts and filename parts respectively.

For the target lib ( member .o) and the s2.a rule, the internal macros are defined as:

$<

member .s2

$*

member

$@

lib

$?

member .s2

$%

member .o

Default Rules

The default rules for make achieve results that are the same as if the following were used. Implementations that do not support FORTRAN may omit FC , FFLAGS and the .f inference rules. Implementations may provide additional macros and rules.

SPECIAL TARGETS

.SCCS_GET: sccs $(SCCSFLAGS) get $(SCCSGETFLAGS) $@

.SUFFIXES: .o .c .y .l .a .sh .f .c~ .y~ .l~ .sh~ .f~

MACROS

MAKE=make
AR=ar
ARFLAGS=-rv
YACC=yacc
YFLAGS=
LEX=lex
LFLAGS=
LDFLAGS=
CC=c89
CFLAGS=-O
FC=fort77
FFLAGS=-O 1
GET=get
GFLAGS=
SCCSFLAGS=
SCCSGETFLAGS=-s

SINGLE SUFFIX RULES

.c:
    $(CC) $(CFLAGS) $(LDFLAGS) -o $@ $<

.f:
    $(FC) $(FFLAGS) $(LDFLAGS) -o $@ $<

.sh:
    cp $< $@
    chmod a+x $@

.c~:
    $(GET) $(GFLAGS) -p $< > $*.c
    $(CC) $(CFLAGS) $(LDFLAGS) -o $@ $*.c

.f~:
    $(GET) $(GFLAGS) -p $< > $*.f
    $(FC) $(FFLAGS) $(LDFLAGS) -o $@ $*.f

.sh~:
    $(GET) $(GFLAGS) -p $< > $*.sh
    cp $*.sh $@
    chmod a+x $@

DOUBLE SUFFIX RULES

.c.o:
    $(CC) $(CFLAGS) -c $<

.f.o:
    $(FC) $(FFLAGS) -c $<

.y.o:
    $(YACC) $(YFLAGS) $<
    $(CC) $(CFLAGS) -c y.tab.c
    rm -f y.tab.c
    mv y.tab.o $@

.l.o:
    $(LEX) $(LFLAGS) $<
    $(CC) $(CFLAGS) -c lex.yy.c
    rm -f lex.yy.c
    mv lex.yy.o $@

.y.c:
    $(YACC) $(YFLAGS) $<
    mv y.tab.c $@

.l.c:
    $(LEX) $(LFLAGS) $<
    mv lex.yy.c $@

.c~.o:
    $(GET) $(GFLAGS) -p $< > $*.c
    $(CC) $(CFLAGS) -c $*.c

.f~.o:
    $(GET) $(GFLAGS) -p $< > $*.f
    $(FC) $(FFLAGS) -c $*.f

.y~.o:
    $(GET) $(GFLAGS) -p $< > $*.y
    $(YACC) $(YFLAGS) $*.y
    $(CC) $(CFLAGS) -c y.tab.c
    rm -f y.tab.c
    mv y.tab.o $@

.l~.o:
    $(GET) $(GFLAGS) -p $< > $*.l
    $(LEX) $(LFLAGS) $*.l
    $(CC) $(CFLAGS) -c lex.yy.c
    rm -f lex.yy.c
    mv lex.yy.o $@

.y~.c:
    $(GET) $(GFLAGS) -p $< > $*.y
    $(YACC) $(YFLAGS) $*.y
    mv y.tab.c $@

.l~.c:
    $(GET) $(GFLAGS) -p $< > $*.l
    $(LEX) $(LFLAGS) $*.l
    mv lex.yy.c $@

.c.a:
    $(CC) -c $(CFLAGS) $<
    $(AR) $(ARFLAGS) $@ $*.o
    rm -f $*.o

.f.a:
    $(FC) -c $(FFLAGS) $<
    $(AR) $(ARFLAGS) $@ $*.o
    rm -f $*.o